Memory controller, memory system including the same, and operation method thereof

A memory system, comprising:

• a memory device that includes a plurality of memory cells;
• and
• a memory controller suitable for reading a data stored in the memory device in response to a read command and performing a first Error Correction Code (ECC) encoding onto the read data to produce a first ECC encoded data,
• wherein the memory controller counts a write command to produce a counted data, performs a second ECC encoding onto the counted data in response to a send command to produce a second ECC encoded data, and outputs the first ECC encoded data and the second ECC encoded data as a read data.

A method for operating a memory system, comprising:

• performing a counting operation in response to a write command to produce a counted data;
• reading a data from a memory device in response to a read command;
• performing a first Error Correction Code (ECC) encoding onto the read data to produce a first ECC encoded data;
• performing a second ECC encoding onto the counted data in response to a send command to produce a second ECC encoded data;
• and
• combining the first ECC encoded data with the second ECC encoded data to output a read data.

A memory system, comprising:

• a memory device for storing data;
• and
• a memory controller suitable for:
• performing a first ECC encoding on a data transferred from the memory device, in response to a read command;
• and
• performing a second ECC encoding on a counted data regarding a write command, in response to a send command, to generate a read data including results of the first and second ECC encodings.