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US 2019/0165808 A1Published application
Memory device including parity error detection circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsHye-Seung YU, Sukyong KANG, Wonjoo YUN, Hyunui LEE, Jae-Hun JUNG
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Abstract
A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.
Claims6
A memory device comprising:
- an aligner configured to sample data by a data strobe signal, the data strobe signal not including a post-amble;
- and
- a parity error detection circuit configured to,
- perform parity check on the data sampled by the aligner to generate a parity error signal, and
- output the parity error signal during a time period determined according to a burst length of the data, the parity error signal indicating whether a parity error is generated in the data based on results of the parity check.
2 more elements
Dependencies are inferred from the claim text.