Multiplying DAC of pipelined ADC

A multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (ADC) and operating in a sampling phase or an amplification phase, comprising:

• an operational amplifier
• a first capacitor having a first end and a second end, wherein the first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase;
• a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase;
• a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase;
• and
• a fourth capacitor having a seventh end and an eighth end, wherein the seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase;
• wherein the DC voltages of the first and second input terminals of the operational amplifier in the amplification phase are not substantially equal to the first reference voltage.

A multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (ADC) and operating in a sampling phase or an amplification phase, comprising:

• an operational amplifier;
• a first capacitor having a first end and a second end, wherein the first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase;
• a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase;
• a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase;
• a fourth capacitor having a seventh end and an eighth end, wherein the seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase;
• a fifth capacitor having a ninth end and a tenth end, wherein the ninth end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the tenth end receives the differential input signal in the sampling phase and is coupled to a common-mode voltage of the second reference voltage and the third reference voltage in the amplification phase;
• and
• a sixth capacitor having an eleventh end and a twelfth end, wherein the eleventh end is coupled to the first reference voltage in the sampling phase, and is coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the twelfth end receives the differential input signal in the sampling phase and is coupled to the common-mode voltage in the amplification phase.