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US 2019/0165770 A1Published application
Level shift circuit and display driver integrated circuit
AssigneeSharp Kabushiki Kaisha
InventorKANAME YAMANO
Life of this patent
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Abstract
A level shift block of a level shift circuit includes a level shifter by which an amplitude level of a signal to drive a P-type transistor is extended to a negative side, and a level shifter by which an amplitude level of a signal to drive an N-type transistor is extended to a positive side.
Claims8
A level shift circuit comprising
- an output buffer circuit composed of a P-type transistor and an N-type transistor that output a signal, wherein
- a level of a gate signal with which the P-type transistor is turned on is an electric potential lower than an electric potential of a negative-side power source of the output buffer circuit, and
- a level of a gate signal with which the N-type transistor is turned on is an electric potential higher than an electric potential of a positive-side power source of the output buffer circuit.
A level shift circuit comprising:
- a level shift block by which a level of a logic signal is shifted;
- and
- an output buffer circuit including a P-type transistor and an N-type transistor that output a signal, wherein
- the level shift block includes a first level shifter by which an amplitude level of a signal to drive the P-type transistor is extended to a negative side, and a second level shifter by which an amplitude level of a signal to drive the N-type transistor is extended to a positive side.
1 more element
Dependencies are inferred from the claim text.