On-chip diplexer

An on-chip diplexer circuit deployed within a semiconductor package, comprising:

• at least a first, a second, a third and a fourth layers;
• a low pass filter (LPF) deployed on the second, the third and the fourth layers;
• a first inductance and capacitance (LC) resonator unit for providing a first resonant frequency deployed on the second and the third layers;
• a second inductance and capacitance (LC) resonator unit for providing a second resonant frequency deployed on the third and the fourth layers, wherein the first resonant frequency is lower than the second resonant frequency;
• and
• a high pass filter (HPF) deployed on the second, the third and the fourth layers.

A method for constructing an on-chip diplexer circuit using Chip On Wafer On Substrate (CoWos), the method comprising:

• deploying a first layer (M1), a second layer (M2), a third layer (M3) and a fourth layer (M4);
• constructing a low pass filter by constructing a first capacitor in the M2 layer, a second capacitor in the M2 layer and a first inductor in the M3 and M4 layers;
• constructing a first inductance and capacitance (LC) resonator for providing a first resonant frequency by constructing a third capacitor in the M2 layer, and a second inductor in the M3 layer;
• constructing a second inductance and capacitance (LC) resonator for providing a second resonant frequency that is higher than the first resonant frequency by constructing a fourth capacitor in the M4 layer and a third inductor in the M3 layer;
• and
• constructing a high pass filter by constructing a fifth capacitor in the M4 layer, a fourth inductor in the M2 layer and a fifth inductor in the M2 layer.