Regulator Control Integrated Circuit Having COT and Valley Current Modes

A voltage regulator control integrated circuit having a valley current (VC) mode and a constant on-time (COT) mode, the voltage regulator control integrated circuit comprising:

• a sequential logic element having a set input lead, a reset input lead, and an output lead;
• a comparator circuit that supplies a set signal SET to the sequential logic element;
• a osc/one-shot circuit that supplies a reset signal RESET to the sequential logic element, wherein in the COT mode the reset signal RESET is a delayed one-shot pulse signal, and wherein in the VC mode the reset signal RESET is a free-running oscillating signal;
• a compensation signal generator circuit that supplies a compensation voltage signal VC to the comparator circuit, wherein in the COT mode the compensation voltage signal VC is an AC ground signal, and wherein in the VC mode the compensation voltage signal VC is a ramp signal;
• a current sense circuit that outputs a voltage signal VCURRENT indicative of a magnitude of a current, wherein the current sense circuit supplies the voltage signal VCURRENT to the comparator circuit;
• and
• an error amplifier circuit that supplies an error voltage signal VE to the comparator circuit, wherein the compensation signal generator circuit comprises a ramp signal generator and a switch, wherein in the VC mode the switch is switched to receive the ramp signal from the ramp signal generator and to output the ramp signal onto a switch output node, and wherein in the COT mode the switch is switched to couple the switch output node to an AC ground node.

A voltage regulator control integrated circuit having a valley current (VC) mode and a constant on-time (COT) mode, the voltage regulator control integrated circuit comprising:

• a sequential logic element having a set input lead, a reset input lead, and an output lead;
• a comparator circuit that supplies a set signal SET to the sequential logic element;
• a osc/one-shot circuit that supplies a reset signal RESET to the sequential logic element, wherein in the COT mode the reset signal RESET is a delayed one-shot pulse signal, and wherein in the VC mode the reset signal RESET is a free-running oscillating signal;
• a compensation signal generator circuit that supplies a compensation voltage signal VC to the comparator circuit, wherein in the COT mode the compensation voltage signal VC is an AC ground signal, and wherein in the VC mode the compensation voltage signal VC is a ramp signal;
• a current sense circuit that outputs a voltage signal VCURRENT indicative of a magnitude of a current, wherein the current sense circuit supplies the voltage signal VCURRENT to the comparator circuit;
• and
• an error amplifier circuit that supplies an error voltage signal VE to the comparator circuit, wherein the osc/one-shot circuit comprises a one-shot circuit, an oscillator, and a switch, wherein in the VC mode the switch is switched to receive the free-running oscillating signal from the oscillator and to output the free-running oscillating signal onto a switch output node, and wherein in the COT mode the switch is switched to receive a delayed one-shot pulse signal from the one-shot circuit and to output the delayed one-shot pulse signal onto the switch output node.

An integrated circuit having a valley current (VC) mode and a constant on-time (COT) mode, the integrated circuit comprising:

• an error amplifier circuit adapted to receive a feedback signal FB;
• a compensation signal generator circuit adapted to output a compensation voltage signal VC, wherein the compensation voltage signal VC is one of a ramp signal and an AC ground signal;
• a comparator circuit adapted to receive an error voltage signal VE from the error amplifier circuit, and adapted to receive the compensation voltage signal VC from the compensation signal generator circuit;
• a osc/one-shot circuit adapted to output a reset signal RESET, wherein the reset signal RESET is one of a free-running oscillating signal and a delayed one-shot pulse signal;
• and
• a sequential logic element adapted to receive a set signal SET from the comparator circuit and adapted to receive the reset signal RESET from the osc/one-shot circuit, wherein the sequential logic element outputs a switch control signal SWC, wherein in the COT mode the integrated error amplifier circuit, the compensation signal generator circuit, the comparator circuit, the osc/one-shot circuit, and the sequential logic element are configured to operate together as a COT mode regulator control circuit, and in the VC mode the integrated error amplifier circuit, the compensation signal generator circuit, the comparator circuit, the osc/one-shot circuit, and the sequential logic element are configured to operate together as a VC mode regulator control circuit.

A voltage regulator control circuit having a valley current (VC) mode and a constant on-time (COT) mode, the voltage regulator control circuit comprising:

• a sequential logic element that has a set state and a reset state;
• a comparator circuit that supplies a set signal SET to the sequential logic element;
• a osc/one-shot circuit that supplies a reset signal RESET to the sequential logic element, wherein in the COT mode the reset signal RESET is a delayed one-shot pulse signal, and wherein in the VC mode the reset signal RESET is a free-running oscillating signal;
• a compensation signal generator circuit that supplies a compensation voltage signal VC to the comparator circuit, wherein in the COT mode the compensation voltage signal VC is an AC ground signal, and wherein in the VC mode the compensation voltage signal VC is a ramp signal;
• a current sense circuit that outputs a voltage signal VCURRENT indicative of a magnitude of a current, wherein the current sense circuit supplies the voltage signal VCURRENT to the comparator circuit;
• and
• an error amplifier circuit that supplies an error voltage signal VE to the comparator circuit.