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US 2019/0165571 A1Published application
Power supply clamp for electrostatic discharge (esd) protection having a circuit for controlling clamp time out behavior
AssigneeSTMicroelectronics International N.V.
InventorsVicky Batra, Radhakrishnan Sithanandam
Life of this patent
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Abstract
Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit formed by an ESD event actuated transistor device. A bias current is generated in response to operation of a voltage independent current generator circuit. The bias current is sourced to ensure that the transistor device is deactuated after the ESD event is dissipated.
Claims23
An electrostatic discharge (ESD) protection circuit, comprising:
- a first power supply line;
- a second power supply line;
- a switching circuit having a first conduction terminal connected to the first power supply line, a second conduction terminal connected to the second power supply line and a gate control terminal;
- a trigger circuit for asserting, in response to detection of an ESD event at one or more of the first and second power supply lines, a trigger signal at the gate terminal of the switching circuit;
- and
- a voltage independent current generator circuit powered from the first and second power supply lines to generate a bias current that controls deasserting of the trigger signal.
3 more elements
An electrostatic discharge (ESD) protection circuit, comprising:
- a first power supply line;
- a second power supply line;
- a switching circuit having a first conduction terminal connected to the first power supply line, a second conduction terminal connected to the second power supply line and a gate control terminal;
- an inverter circuit having an output connected to the gate control terminal of the switching circuit;
- a first transistor having a source-drain path connected between a input of the inverter circuit and the second power supply line and a control gate coupled to receive an ESD detection signal;
- a second transistor having a source-drain path connected between the input of the inverter circuit and the first power supply line and a control gate coupled to receive a bias current control signal;
- an ESD detection circuit configured to assert the ESD detection signal in response to detection of an ESD event;
- and
- a voltage independent current generator circuit powered from the first and second power supply lines and configured to generate the bias current control signal.
6 more elements
Dependencies are inferred from the claim text.