Spacer-based patterning for tight-pitch and low-variability random access memory (ram) bit cells and the resulting structures

A method of fabricating a semiconductor structure, the method comprising:

• forming a hardmask layer above a memory material stack on a top layer of a substrate;
• forming a grating structure in the hardmask layer using a first spacer-based patterning process, the grating structure comprising a plurality of lines along a first direction;
• cutting the plurality of lines along a second direction orthogonal to the first direction using a second spacer-based patterning process to form a twice-patterned hardmask;
• etching the memory material stack using the twice-patterned hardmask as a mask to form an array of non-volatile random access memory (RAM) bit cells from the memory material stack, the array of non-volatile RAM bit cells comprising columns of non-volatile RAM bit cells along the first direction and rows of non-volatile RAM bit cells along the second direction, wherein the etching forms a plurality of recesses in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

A method of fabricating a semiconductor structure, the method comprising:

• forming a hardmask layer above a memory material stack on a top layer of a substrate;
• forming a grating structure in the hardmask layer using a first spacer-based patterning process, the grating structure comprising a plurality of lines along a first direction;
• cutting the plurality of lines along a second direction orthogonal to the first direction using a second spacer-based patterning process to form a twice-patterned hardmask;
• etching the memory material stack using the twice-patterned hardmask as a mask to form an array of non-volatile random access memory (RAM) bit cells from the memory material stack, the array of non-volatile RAM bit cells comprising columns of non-volatile RAM bit cells along the first direction and rows of non-volatile RAM bit cells along the second direction, wherein the etching forms, from a plan view perspective, substantially straight edges along the first direction and along the second direction and substantially rounded corners joining the straight edges for each of the non-volatile RAM bit cells of the array of non-volatile RAM bit cells.