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US 2019/0165186 A1Published application
Semiconductor chip
AssigneeSocionext Inc.
InventorHiroyuki SHIMBO
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.
Claims8
A semiconductor chip, comprising:
- a first block including a standard cell having a nanowire field effect transistor (FET);
- and
- a second block including a nanowire PET,
- wherein
- the nanowire FETs included in the first and second blocks each include:
- a nanowire extending in a first direction, the nanowire being a single nanowire or including a plurality of parallelly arranged nanowires;
- a pair of pads that are arranged at both ends of the nanowire in the first direction, each have a lower surface below a lower surface of the nanowire, and are each connected to the nanowire;
- and
- a gate electrode that extends in a second direction perpendicular to the first direction, and surrounds a periphery of the nanowire within a predetermined range of the nanowire in the first direction,
- in the first and second blocks,
- the nanowires have an arrangement pitch in the second direction of an integer multiple of a predetermined first pitch, and
- the pads have an arrangement pitch in the first direction of an integer multiple of a predetermined second pitch.
9 more elements
A semiconductor chip, comprising:
- a first block including a standard cell having a nanowire field effect transistor (FET);
- and
- a second block including a nanowire FET,
- wherein
- the nanowire FETs included in the first and second blocks each include:
- a nanowire extending in a first direction, the nanowire being a single nanowire or including a plurality of parallelly arranged nanowires;
- a pair of pads that are respectively arranged at both ends of the nanowire in the first direction, each have a lower surface below a lower surface of the nanowire, and are each connected to the nanowire;
- and
- a gate electrode that extends in a second direction perpendicular to the first direction, and surrounds a periphery of the nanowire within a predetermined range of the nanowire in the first direction,
- in at least one of the nanowire FETs included in the first and second blocks, the nanowires are arranged in a third direction perpendicular to the first direction and the second direction, and
- in the first and second blocks, the nanowires have an arrangement pitch in the second direction of an integer multiple of a predetermined first pitch and have an arrangement pitch in the third direction of an integer multiple of a predetermined nanowire stack pitch.
8 more elements
Dependencies are inferred from the claim text.