Metal rail conductors for non-planar semiconductor devices

An integrated circuit, comprising:

• a dielectric region;
• and
• a first fin field-effect transistor (finFET), having a first source region, a first gate region, and a first drain region, situated onto the dielectric region and a first fin structure protruding from the dielectric region;
• a second finFET having a second source region, a second gate region, and a second drain region, situated onto the dielectric region and a second fin structure protruding from the dielectric region;
• and
• a rail conductor situated within the dielectric region, the rail conductor being electrically connected to first and second terminal regions selected from among the first source region, the first gate region, the first drain region, the second source region, the second gate region, or the second drain region.

A fin field-effect transistor (finFET) array, comprising:

• a semiconductor substrate;
• a dielectric region situated above the semiconductor substrate;
• a plurality of source regions situated onto the dielectric region;
• a plurality of gate regions situated onto the dielectric region;
• a plurality of drain regions situated onto the dielectric region;
• a fin structure situated onto the semiconductor substrate and traversing through the dielectric region, the fin structure being configured to be between the plurality of source regions and the plurality of drain regions and to traverse through the plurality of gate regions;
• and
• a rail conductor situated within the dielectric region, the rail conductor being electrically connected to a first terminal region selected from among the plurality of source regions, the plurality of gate regions, and plurality of the drain regions,
• wherein the rail conductor is configured to be parallel to the fin structure and to be extend a horizontal length of the semiconductor substrate.