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US 2019/0165168 A1Published application
LDMOS Transistor with Segmented Gate Dielectric Layer
AssigneeTexas Instruments Incorporated
InventorsSameer Pendharkar, Ming-yeh Chuang
Life of this patent
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Abstract
A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit.
Claims20
A transistor device, comprising:
- a semiconductor substrate having a surface;
- a source region stripe extending into the semiconductor substrate from the surface;
- a drain region stripe extending into a body region within the semiconductor substrate from the surface, the drain region stripe spaced apart from and arranged substantially parallel to the source region stripe;
- a conductive gate structure located between the source region stripe and the drain region stripe, the gate structure comprising a plurality of first gate regions in which the gate is spaced apart from the body region by a first distance, and a plurality of second gate regions in which the gate is spaced apart from the body region by a second greater distance, the first gate regions being interleaved with the second gate regions.
1 more element
The transistor device of claim 8, wherein the width is less than the distance between an adjacent pair of the gate dielectric segments.
An integrated circuit, comprising:
- a semiconductor substrate having a surface;
- and
- a plurality of transistor devices formed within or over the substrate, each transistor device including:
- a source region stripe extending into the semiconductor substrate from the surface;
- a drain region stripe extending into a body region within the semiconductor substrate from the surface, the drain region stripe spaced apart from and arranged substantially parallel to the source region stripe;
- a conductive gate structure located between the source region stripe and the drain region stripe, the gate structure comprising a plurality of first gate regions in which the gate is spaced apart from the body region by a first distance, and a plurality of second gate regions in which the gate is spaced apart from the body region by a second greater distance, the first gate regions being interleaved with the second gate regions.
3 more elements
A transistor device, comprising:
- a semiconductor substrate having a surface;
- a first doped stripe region located within the substrate and doped a first conductivity type;
- a second doped stripe region located within the substrate and doped the first conductivity type;
- a third doped stripe region doped a second different conductivity type, the second doped stripe region being located at least partially within the third doped stripe region;
- a conductive gate electrode located between the first doped region stripe and the second doped region stripe, the gate electrode comprising a plurality of first gate electrode regions interleaved with a second plurality of second gate electrode regions, the first gate electrode regions being spaced apart from the third doped stripe region by a first distance, and the second gate electrode regions being spaced apart from the third doped stripe region by a second greater distance.
2 more elements
Dependencies are inferred from the claim text.