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US 2019/0165163 A1Published application
Semiconductor device
AssigneeFuji Electric Co., Ltd.
InventorsYusuke KOBAYASHI, Manabu TAKEI, Shinsuke HARADA, Naoyuki OHSE
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Abstract
A vertical MOSFET having a trench gate structure includes an n−-type drift layer and a p-type base layer formed by epitaxial growth. In the n−-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.
Claims6
A semiconductor device comprising:
- a semiconductor substrate of a first conductivity type;
- a first semiconductor layer of the first conductivity type provided on a front surface of the semiconductor substrate and having an impurity concentration that is lower than an impurity concentration of the semiconductor substrate;
- a plurality of first semiconductor regions of a second conductivity type selectively provided in the first semiconductor layer;
- a second semiconductor layer of the second conductivity type provided on a first side of the first semiconductor layer, opposite a second side of the first semiconductor layer facing toward the semiconductor substrate;
- a second semiconductor region of the first conductivity type selectively provided in the second semiconductor layer and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate;
- a first trench penetrating the second semiconductor region and the second semiconductor layer, and reaching the first semiconductor layer, a bottom of the first trench being in contact with a first first-semiconductor-region of the plurality of first semiconductor regions;
- a second trench penetrating the second semiconductor layer and reaching the first semiconductor layer, a bottom of the second trench being in contact with a second first-semiconductor-region of the plurality of first semiconductor regions;
- a gate electrode provided in the first trench, via a gate insulating film;
- and
- a Schottky electrode provided in the second trench, wherein
- the plurality of first semiconductor regions are provided with an interval therebetween along a width direction of the first trench, in a region opposing, in a depth direction, a gate electrode pad connected to the gate electrode.
8 more elements
Dependencies are inferred from the claim text.