Gate patterning for quantum dot devices

A method of operating a quantum dot device, comprising:

• applying one or more voltages to one or more gates on a first quantum well stack region to cause a first quantum dot to form in a second quantum well stack region;
• applying one or more voltages to one or more gates on the second quantum well stack region to cause a second quantum dot to form in the second quantum well stack region;
• and
• sensing a quantum state of the first quantum dot with the second quantum dot;
• wherein the one or more gates on the first quantum well stack region include two first gates having a first length, a second gate disposed between the two first gates and having a second length different from the first length, two third gates having a third length and arranged such that the first gates are disposed between the third gates, and wherein the third length is different from the first length and from the second length.

A method of manufacturing a quantum dot device, comprising:

• providing a quantum well stack on a substrate;
• providing a gate stack on the quantum well stack, wherein the gate stack includes a first hardmask;
• providing a second hardmask on the first hardmask;
• providing a resist on the second hardmask;
• patterning the resist to form first resist portions;
• providing first template material over the first resist portions;
• etching the first template material to form patterned first template material on sides of the first resist portions;
• after etching the first template material, removing the first resist portions;
• after removing the first resist portions, patterning the second hardmask;
• after etching the second hardmask, removing the first template material;
• after removing the first template material, providing second template material over the patterned second hardmask;
• etching the second template material to form patterned second template material on sides of the patterned second hardmask;
• after etching the second template material, removing the patterned second hardmask;
• and
• patterning the gate stack to form gates in accordance with the patterned second template material.

A quantum computing device, comprising:

• a quantum processing device, wherein the quantum processing device includes a first set of gates over a first quantum well stack region in parallel with a second set of gates over a second quantum well stack region, an active quantum well layer in the first quantum well stack region, and a read quantum well layer in the second quantum well stack region, wherein the first set of gates includes two first gates having a first length, a second gate disposed between the two first gates and having a second length different from the first length, two third gates having a third length and arranged such that the first gates are disposed between the third gates, and wherein the third length is different from the first length and from the second length;
• a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the first set of gates and the second set of gates;
• and
• a memory device to store data generated by the read quantum well layer during operation of the quantum processing device.