US 2019/0165145 A1 · FIN TRIM ISOLATION WITH SINGLE GATE SPACING FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins, individual ones of the plurality of fins along a first direction. A plurality of gate structures is formed over the plurality of fins, individual ones of the gate structures along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of one of the plurality of gate structures is removed to expose a portion of each of the plurality of fins. The exposed portion of each of the plurality of fins is removed. An insulating layer is formed in locations of the removed portion of each of the plurality of fins.

Claims21

Dependent claims

A method of fabricating an integrated circuit structure, the method comprising:

forming a plurality of fins, individual ones of the plurality of fins along a first direction;
forming a plurality of gate structures over the plurality of fins, individual ones of the gate structures along a second direction orthogonal to the first direction;
forming a dielectric material structure between adjacent ones of the plurality of gate structures;
removing a portion of one of the plurality of gate structures to expose a portion of each of the plurality of fins;
removing the exposed portion of each of the plurality of fins;
and
forming an insulating layer in locations of the removed portion of each of the plurality of fins.

4 more elements

An integrated circuit structure, comprising:

a fin comprising silicon, the fin having a longest dimension along a first direction;
an isolation structure separating a first upper portion of the fin from a second upper portion of the fin along the first direction, the isolation structure having a center along the first direction;
a first gate structure over the first upper portion of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction, wherein a center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction;
a second gate structure over the first upper portion of the fin, the second gate structure having a longest dimension along the second direction, wherein a center of the second gate structure is spaced apart from the center of the first gate structure by the pitch along the first direction;
and
a third gate structure over the second upper portion of the fin, the third gate structure having a longest dimension along the second direction, wherein a center of the third gate structure is spaced apart from the center of the isolation structure by the pitch along the first direction.

3 more elements

A method of fabricating an integrated circuit structure, the method comprising:

forming a fin comprising silicon, the fin having a longest dimension along a first direction;
forming an isolation structure separating a first upper portion of the fin from a second upper portion of the fin along the first direction, the isolation structure having a center along the first direction;
forming a first gate structure over the first upper portion of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction, wherein a center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction;
forming a second gate structure over the first upper portion of the fin, the second gate structure having a longest dimension along the second direction, wherein a center of the second gate structure is spaced apart from the center of the first gate structure by the pitch along the first direction;
and
forming a third gate structure over the second upper portion of the fin, the third gate structure having a longest dimension along the second direction, wherein a center of the third gate structure is spaced apart from the center of the isolation structure by the pitch along the first direction.

3 more elements

Dependencies are inferred from the claim text.

Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication

Life of this patent

Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication

Life of this patent

Abstract

Claims21