A method performed to a structure that includes a substrate with a first region configured for logic devices and a second region configured for radio frequency (RF) devices, a first fin over the first region, a first gate structure engaging the first fin, a second fin over the second region, a second gate structure engaging the second fin, and gate spacers over sidewalls of the first and second gate structures, the method comprising:
- forming a first masking element exposing portions of the first fin and covering the second region;
- performing a first etching process to the first fin, thereby resulting in a first recess proximate the first gate structure;
- removing the first masking element;
- forming a second masking element exposing portions of the second fin and covering the first region;
- and
- performing a second etching process to the second fin, resulting in a second recess proximate the second gate structure, wherein the first and second etching processes are tuned to differ in at least one parameter such that the first recess is shallower than the second recess and a first distance between the first recess and the first gate structure along the first fin lengthwise is smaller than a second distance between the second recess and the second gate structure along the second fin lengthwise.