NANOSHEET WITH CHANGING SiGe PERCENTAGE FOR SiGe LATERAL RECESS

A semiconductor device, comprising:

• a plurality of stacked semiconductor structures spaced apart from each other on a semiconductor substrate, wherein each of the plurality of stacked semiconductor structures comprises:
• a stacked configuration of a plurality of gate structures and a plurality of silicon layers on the semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a gate structure;
• a plurality of epitaxial source/drain regions between the plurality of stacked semiconductor structures, wherein the epitaxial source/drain regions extend from sides of the plurality of silicon layers;
• and
• wherein each of the plurality of gate structures has the same or substantially the same width as each other.

A method for manufacturing a semiconductor device, comprising:

• forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer;
• patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other;
• etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers;
• wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other;
• and
• replacing the remaining portions of each of the plurality of silicon germanium layers with respective gate structures having the same or substantially the same width as each other.