Method for manufacturing semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Chen LO, Li-Te LIN, Pinyen LIN
Life of this patent
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Abstract
A method for manufacturing a semiconductor device, includes: forming a dummy gate structure on a semiconductor substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor substrate; forming a metal gate electrode on the semiconductor substrate and between the gate spacers; and performing a plasma etching process to the metal gate electrode, wherein the plasma etching process comprises performing in sequence a first non-zero bias etching step and a first zero bias etching step.
Claims20
A method for manufacturing a semiconductor device, comprising:
- forming a dummy gate structure on a semiconductor substrate;
- forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure;
- removing the dummy gate structure from the semiconductor substrate;
- forming a metal gate electrode on the semiconductor substrate and between the gate spacers;
- and
- performing a plasma etching process to the metal gate electrode, wherein the plasma etching process comprises performing in sequence a first non-zero bias etching step and a first zero bias etching step.
A method for manufacturing a semiconductor device, comprising:
- forming a dummy gate structure on a semiconductor substrate;
- forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure;
- replacing the dummy gate structure with a replacement gate structure;
- etching the replacement gate structure;
- forming a dielectric cap over the etched replacement gate structure and between the gate spacers;
- and
- performing a plasma etching process to the dielectric cap, wherein the plasma etching process comprises performing in sequence a first non-zero bias etching step and a first zero bias etching step.
A semiconductor device, comprising:
- a substrate;
- a plurality of gate spacers over the substrate;
- a gate structure between the gate spacers;
- a dielectric cap atop the gate structure and between the gate spacers;
- and
- a hard mask atop the dielectric cap and between the gate spacers, wherein a bottommost position of the hard mask is not lower than a topmost position of the dielectric cap.
Dependencies are inferred from the claim text.