Semiconductor device and method of manufacturing the same

A semiconductor device, comprising:

• first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis;
• a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure;
• a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure;
• a first spacer comprising:
• a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis;
• and
• a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis;
• and
• a second spacer comprising:
• a first portion comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis;
• and
• a second portion comprising two layers that respectively extend from sidewalls of the first portion of the second spacer toward the opposite directions of the axis,
• wherein a thickness of the first portion of the second spacer is substantially thinner than a thickness of the first portion of the first spacer.

A method for forming a fin field-effect transistor (FinFET), comprising:

• forming first and second fin structures each protruding from an upper boundary surface of an isolation feature;
• forming a first dummy stack traversing a central portion of the first fin structure, and a second dummy stack traversing a central portion of the second fin structure;
• forming a first dielectric layer overlaying the first and second dummy stacks;
• etching a portion of the first dielectric layer that overlays the first dummy stack;
• forming a second dielectric layer overlaying the first and second dummy stacks;
• and
• etching the second dielectric layer to form a first spacer extending along a sidewall of the first dummy stack and a second spacer extending along a sidewall of the second dummy stack, wherein the first and second spacers each comprises both the first and second dielectric layers, wherein the first dielectric layer of the first spacer is substantially thinner than the first dielectric layer of the second spacer.