Semiconductor device and method for manufacturing same

A semiconductor device comprising:

• a semiconductor substrate;
• a gate insulating layer disposed on a surface of the semiconductor substrate;
• a gate electrode disposed on the gate insulating layer;
• an interlayer insulating layer that covers the gate electrode;
• a contact hole that penetrates the gate insulating layer and the interlayer insulating layer, causes a portion of the surface of the semiconductor substrate to be exposed, and includes an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer;
• a metal layer that covers an upper surface of the interlayer insulating layer, the inner surface of the contact hole, and at least part of the portion of the surface of the semiconductor substrate exposed by the contact hole;
• and
• a source line connected, via the contact hole, with at least part of the metal layer that covers the at least part of the portion of the surface of the semiconductor substrate exposed by the contact hole,
• wherein the inner surface of the contact hole faces an opening of the contact hole in a cross-sectional view perpendicular to the surface of the semiconductor substrate,
• the inner surface of the contact hole includes a first inner surface close to the surface of the semiconductor substrate, and a second inner surface close to the opening of the contact hole, and
• an angle formed by the first inner surface of the contact hole and the surface of the semiconductor substrate is smaller than an angle formed by the second inner surface of the contact hole and the surface of the semiconductor substrate.

A method for manufacturing a semiconductor device comprising:

• a first step of providing a semiconductor substrate;
• a second step of forming a gate insulating layer on a surface of the semiconductor substrate;
• a third step of forming a gate electrode on the gate insulating layer;
• a fourth step of covering the gate electrode with an interlayer insulating layer;
• a fifth step of forming a mask layer on the interlayer insulating layer;
• a sixth step of etching the interlayer insulating layer and the gate insulating layer by using the mask layer to form a contact hole that causes a portion of the surface of the semiconductor substrate to be exposed and includes an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer;
• a seventh step of removing the mask layer;
• an eighth step of forming a silicide layer by performing annealing while the portion of the surface of the semiconductor substrate exposed by the contact hole is covered with metal;
• a ninth step of forming a metal layer that covers an upper surface of the interlayer insulating layer, the inner surface of the contact hole, and at least part of the silicide layer;
• and
• a tenth step of forming a source line connected, via the contact hole, with at least part of the metal layer that covers the at least part of the silicide layer,
• wherein the metal layer has a thickness equal to or greater than 35 nm at least at a portion that covers a lower part of the inner surface of the contact hole.

A method for manufacturing a semiconductor device comprising:

• a first step of providing a semiconductor substrate;
• a second step of forming a gate insulating layer on a surface of the semiconductor substrate;
• a third step of forming a gate electrode on the gate insulating layer;
• a fourth step of covering the gate electrode with an interlayer insulating layer;
• a fifth step of forming a mask layer on the interlayer insulating layer;
• a sixth step of etching the interlayer insulating layer and the gate insulating layer by using the mask layer to form a contact hole that causes a portion of the surface of the semiconductor substrate to be exposed and includes an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer;
• a seventh step of removing the mask layer;
• an eighth step of forming a silicide layer by performing annealing while the portion of the surface of the semiconductor substrate exposed by the contact hole is covered with metal;
• a ninth step of forming a metal layer that covers an upper surface of the interlayer insulating layer, the inner surface of the contact hole, and at least part of the silicide layer;
• and
• a tenth step of forming a source line connected, via the contact hole, with at least part of the metal layer that covers the at least part of the silicide layer,
• wherein the inner surface of the contact hole faces an opening of the contact hole in a cross-sectional view perpendicular to the surface of the semiconductor substrate,
• the inner surface of the contact hole includes a first inner surface close to the surface of the semiconductor substrate, and a second inner surface close to the opening of the contact hole, and
• an angle formed by the first inner surface of the contact hole and the surface of the semiconductor substrate is smaller than an angle formed by the second inner surface of the contact hole and the surface of the semiconductor substrate.