Non-planar field effect transistor devices with wrap-around source/drain contacts

A method for fabricating a semiconductor device comprising:

• forming a nanowire stack structure on a semiconductor substrate, wherein the nanowire stack structure comprises a first sacrificial semiconductor layer disposed on the semiconductor substrate, a second sacrificial semiconductor layer disposed on the first sacrificial semiconductor layer, and a semiconductor channel layer disposed on the second sacrificial semiconductor layer;
• forming a first isolation layer on the semiconductor substrate, wherein the first isolation layer comprises a thickness which is substantially equal to a thickness of the first sacrificial semiconductor layer of the nanowire stack structure;
• forming a dummy gate structure over a portion of the nanowire stack structure;
• etching exposed portions of the nanowire stack structure, which are not covered by the dummy gate structure, down to an upper surface of the first sacrificial semiconductor layer of the nanowire stack structure;
• laterally recessing exposed sidewall surfaces of the second sacrificial semiconductor layer to form recesses in sidewalls of the nanowire stack structure, wherein the lateral recessing is performed by etching the second sacrificial semiconductor layer selective to the first sacrificial semiconductor layer and the semiconductor channel layer;
• filling the recesses with dielectric material to form embedded gate sidewall spacers;
• etching away the first sacrificial semiconductor layer of the nanowire stack structure to form an opening that is surrounded by the first isolation layer;
• filling the opening with an insulating material to form a second isolation layer;
• forming a first recess region in the first and second isolation layers on a first side of the gate structure, and forming a second recess region in the first and second isolation layers on the second side of the gate structure;
• filling the first and second recess regions with a sacrificial material which has etch selectivity with respect to the first and second isolation layers, to form first and second dummy source/drain contact layers;
• forming a first source/drain region and a second source/drain region over the first dummy source/drain contact layer and the second dummy source/drain contact layer, respectively;
• replacing the dummy gate structure with a metal gate structure;
• etching away the first and second dummy source/drain contact layers selective to the first and second isolation layers to form first and second recesses below the first and second source/drain regions;
• and
• depositing a layer of metallic material to fill the first and second recesses with metallic material and form first and second source/drain contacts which surround the first and second source/drain regions, respectively.

A semiconductor device, comprising:

• a non-planar field effect transistor (FET) device formed on a semiconductor substrate, wherein the non-planar FET device comprises a semiconductor channel layer, and a gate structure in contact with at least an upper surface and sidewall surfaces of the semiconductor channel layer;
• a first source/drain region disposed adjacent to a first side of the gate structure and in contact with the semiconductor channel layer;
• a second source/drain region disposed adjacent to a second side of the gate structure, opposite the first side of the gate structure, and in contact with the semiconductor channel layer;
• a first recess formed in an isolation layer below a bottom surface of the first source/drain region;
• a second recess formed in the isolation layer below a bottom surface of the second source/drain region;
• a first source/drain contact formed in contact with an upper surface, sidewalls surfaces, and the bottom surface of the first source/drain region;
• and
• a second source/drain contact formed in contact with an upper surface, sidewalls surfaces, and the bottom surface of the second source/drain region;
• wherein the first and second source/drain contacts comprise metallic material that is disposed within the first and second recesses in the isolation layer to make contact with the bottom surfaces of the first and second source/drain regions.