Group iii-n nanowire transistors

A semiconductor structure, comprising:

• a nanowire disposed above a substrate, wherein a longitudinal length of the nanowire comprises:
• a channel region of a group III-N material;
• a source region electrically coupled with a first end of the channel region;
• and
• a drain region electrically coupled with a second end of the channel region;
• a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region of the nanowire;
• and
• a semiconductor material beneath the source region and the drain region of the nanowire, wherein the semiconductor material is not included beneath the channel region of the nanowire.

A method of fabricating a semiconductor structure, the method comprising:

• forming a first semiconductor material on a second semiconductor material above a substrate, wherein the first semiconductor material comprises a group III-N material;
• forming a fin from the first semiconductor material and the second semiconductor material;
• forming an insulating layer over the fin;
• forming a gate trench in the insulating layer;
• removing the second semiconductor material from portions of the fin exposed by the gate trench to provide a nanowire having a channel region comprising the group III-N material;
• forming a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region of the nanowire;
• subsequent to forming the gate stack, removing remaining portions of the insulating layer to expose a source region electrically coupled with a first end of the channel region of the nanowire and to expose a drain region electrically coupled with a second end of the channel region of the nanowire, wherein the second semiconductor material is beneath the source and drain regions of the nanowire.