Integrated circuit comprising components, for example nmos transistors, having active regions with relaxed compressive stresses
AssigneeSTMicroelectronics (Rousset) SAS
InventorsGuilhem BOUTON, Pascal FORNARA, Christian RIVERO
Life of this patent
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Abstract
An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
Claims4
A method for fabricating at least one component unfavorably sensitive to compressive stress, comprising:
- producing, in a semiconductor substrate an insulating region delimiting an active region of the semiconductor substrate;
- producing at least one component unfavorably sensitive to compressive stress at least partially in the active region, wherein the at least one component unfavorably sensitive to compressive stresses is an NMOS transistor belonging to a control unit of a memory plane of an integrated memory device, the memory plane having nonvolatile memory cells and selection transistors with buried gates;
- and
- forming at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region;
- wherein forming the at least one electrically inactive trench is carried out simultaneously with forming the buried gates.
A circuit, comprising:
- a semiconductor substrate;
- an insulating region delimiting an active region of the semiconductor substrate;
- at least one component unfavorably sensitive to compressive stress at least partially in the active region, wherein the at least one component unfavorably sensitive to compressive stresses is an NMOS transistor belonging to a control unit of a memory plane of an integrated memory device, the memory plane having nonvolatile memory cells and selection transistors with buried gates;
- at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region;
- wherein the at least one electrically inactive trench and the buried gates have a same depth within the semiconductor substrate.
Dependencies are inferred from the claim text.