Circuit structure and method for reducing electronic noises
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Hung Kao, Chi-Feng Huang, Fu-Huan Tsai, Victor Chiang Liang
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Abstract
In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.
Claims20
An integrated circuit (IC) device, comprising:
- a semiconductor substrate;
- an isolation region and an active region disposed on the semiconductor substrate, wherein the active region is at least partially surrounded by the isolation region;
- a gate stack disposed over the active region;
- and
- a source and a drain disposed in the active region and interposed by the gate stack in a first direction;
- wherein a middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.
An integrated circuit (IC) device, comprising:
- a semiconductor substrate;
- an isolation feature disposed on the semiconductor substrate;
- and
- a field-effect transistor disposed on the semiconductor substrate, wherein the field-effect transistor comprises:
- a channel region adjacent the isolation feature;
- a source and a drain separated by the channel region;
- a gate stack over the channel region;
- and
- a low density doped (LDD) feature disposed on the channel region and adjacent an edge portion of the gate stack, the LDD feature separating the edge portion of the gate stack from the isolation feature.
A method for semiconductor fabrication, comprising:
- providing a semiconductor structure including a substrate, an isolation region on the substrate, and an active region that is at least partially surrounded by the isolation region;
- forming a gate stack over the active region, the gate stack including a gate dielectric layer and a gate electrode layer disposed above the gate dielectric layer;
- forming a low density doped (LDD) feature that separates an edge portion of the gate dielectric layer from the isolation region;
- and
- forming a spacer on sidewalls of the gate stack directly above the LDD feature.
Dependencies are inferred from the claim text.