Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device having a semiconductor layer, comprising the steps of:

• (a) forming on the semiconductor layer,
• a first parallel pn layer including one or more layers, an uppermost layer of which has a first region and a second region having a thickness less than that of the first region, and
• a second parallel pn layer adjacent to the first region and in a surface layer of the uppermost layer in the first parallel pn layer, each layer in the first parallel pn layer having a plurality of first pairs of semiconductor regions, each first pair including a first first-conductivity-type semiconductor region and a first second-conductivity-type semiconductor region, the first first-conductivity-type semiconductor regions and first second-conductivity-type semiconductor regions of said first pairs being alternately and repeatedly arranged with a repetition pitch in a first direction in a first plane parallel to a surface of the substrate, the second parallel pn layer having a plurality of second pairs of semiconductor regions, each second pair including a second first-conductivity-type semiconductor region and a second second-conductivity-type semiconductor region, the second first-conductivity-type semiconductor regions and second second-conductivity-type semiconductor regions being alternately and repeatedly arranged with the repetition pitch in the first direction, in a second plane parallel to said surface of the substrate, a position of each second pair of semiconductor regions in the first direction being shifted by half of the repetition pitch with respect to a position of each first pair of semiconductor regions, the step (a) including:
• (a-1) repeatedly performing one set of steps with at least a first repetition and a last repetition, the one set of steps including
• (a-1-1) depositing on an uppermost surface of the device, an epitaxial layer undoped or of a first conductivity type and having an impurity concentration lower than that of the semiconductor layer,
• (a-1-2) first ion implanting of the first-conductivity-type impurity in the epitaxial layer, and
• (a-1-3) second ion implanting of the second-conductivity-type impurity selectively in the epitaxial layer,
• the last repetition of the step (a-1-2) including respectively performing, in a first epitaxial layer constituting the uppermost layer in the first parallel pn layer,
• ion implanting for forming the first first-conductivity-type semiconductor regions of the first pairs of semiconductor regions of the uppermost layer in the first parallel pn layer, and
• ion implanting for forming the second first-conductivity-type semiconductor regions of the second pairs of semiconductor regions,
• the last repetition of the step (a-1-3) including respectively performing, in the first epitaxial layer,
• ion implanting for forming the first second-conductivity-type semiconductor regions of said first pairs of the uppermost layer in the first parallel pn layer, and
• ion implanting for forming the second second-conductivity-type semiconductor regions of said second pairs;
• and
• (a-2) forming on the first epitaxial layer, a second epitaxial layer undoped or of the first conductivity type and having an impurity concentration lower than that of the semiconductor layer;
• (b) forming a trench in the first first-conductivity-type semiconductor region of one of the first pairs of the semiconductor regions, the trench being formed to extend from said first first-conductivity-type semiconductor region to the second second-conductivity-type semiconductor region of one of the second pairs of the semiconductor regions, terminating at said second second-conductivity-type semiconductor region;
• (c) forming a gate insulating film and a gate electrode on the gate insulating film in the trench, the gate electrode being formed to extend from inside to outside the trench and to remain over a surface of the second parallel pn layer with the gate insulating film therebetween;
• (d) forming a first semiconductor portion of a second conductivity type in a surface layer of the uppermost layer in the first parallel pn layer;
• (e) selectively forming a second semiconductor portion of the first conductivity type in a surface layer of the first semiconductor portion;
• (f) forming a first electrode electrically connected to the first semiconductor portion and the second semiconductor portion;
• and
• (g) forming a second electrode electrically connected to the semiconductor layer.