One-time programmable devices using gate-all-around structures

An electronics system, comprising:

• a processor;
• and
• an OTP memory operatively connected to the processor, the OTP memory includes at least a plurality of OTP cells for providing data storage, each of the OTP cells comprising:
• a resistive element;
• and
• at least one nano-wire structure residing on an isolated substrate;
• the at least one nano-wire being covered by at least one MOS gate all around (GAA) to divide the at least one nano-wires into at least a first active region and a second active region, the first active region having a first type of dopant, and the second active region having the first type of dopant or a second type of dopant;
• the first active region coupled to the resistive element, the other end of the resistive element coupled to a first voltage supply line, the second active region coupled to a second voltage supply line, and the gate coupled to a third voltage supply line,
• wherein the first and/or the second active region of the nano-wires are coupled together by extended source/drain, and
• wherein the resistive element can be configured to be programmable into a different resistance state by applying voltages to the first, second, and the third voltage supply lines.

A method for providing an One-Time Programmable (OTP) memory, comprising:

• providing a plurality of OTP cells, at least one of the OTP cells includes at least (i) a resistive element coupled to a first supply voltage line;
• and (ii) at least one nano-wire structure having at least one active region divided by at least one MOS gate all around (GAA) into at least a first active region and a second active region, the first active region having a first type of dopant and the second region having a first or second type of dopant, both the first and second active regions being fabricated from sources or drains of CMOS devices, (iii) both the first and second active regions residing on an isolated substrate, (iv) at least one of the first or the second active regions are coupled together by at least one extended source/drain, and (v) the first active region coupled to the resistive element and the second active region coupled to a second supply voltage line;
• the MOS gate coupled to a third supply voltage line;
• and
• programming a logic state into at least one of the OTP cells by applying voltages to the first, second, and/or third voltage lines.

An One-Time Programmable (OTP) memory, comprising:

• a plurality of OTP cells, at least one of the OTP cells comprising:
• a resistive element;
• at least one nano-wire structure residing on an isolated substrate, the nano-wire structure including a plurality of nano-wires, at least one of the plurality of nano-wires being covered by at least one MOS gate all around (GAA) to divide the at least one of the plurality of nano-wires into at least a first active region and a second active region, the first active region coupled to one end of the resistive element, the other end of the resistive element coupled to a first voltage supply line, the second active region coupled to a second voltage supply line, and the MOS gate coupled to a third voltage supply line,
• wherein the first and/or the second active regions of two or more of the plurality of nano-wires are coupled together by at least one extended source/drain, and
• wherein the resistive element can be configured to be programmable into a different resistance state by applying voltages to the first, second, and the third voltage supply lines.