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US 2019/0165044 A1Published application
Vertical thin film transistors with isolation
AssigneeSanDisk Technologies LLC
InventorSeje Takaki
Life of this patent
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Abstract
A method is provided that includes forming a transistor by forming a gate dielectric layer above a substrate, forming a spacer dielectric layer above the gate dielectric layer, and forming a gate adjacent the gate dielectric layer and above the spacer dielectric layer.
Claims20
A method comprising:
- forming a transistor by:
- forming a gate dielectric layer above a substrate;
- forming a spacer dielectric layer above the gate dielectric layer;
- forming a liner material layer between the gate dielectric layer and the spacer dielectric layer;
- and
- after forming the liner material layer, forming a gate adjacent the gate dielectric layer and above the spacer dielectric layer.
3 more elements
(canceled)
A method comprising:
- forming a vertically-oriented bit-line select transistor by:
- forming a spacer dielectric layer disposed between a transistor control terminal and a conductor disposed below the vertically-oriented bit line select transistor;
- forming a liner material layer between a gate dielectric layer and the spacer dielectric layer;
- and
- forming the transistor control terminal after forming the liner material layer.
2 more elements
Apparatus comprising:
- a first vertically-oriented bit line select transistor above a substrate, the first vertically-oriented bit line select transistor comprising a first gate and a gate dielectric layer;
- a second vertically-oriented bit line select transistor above a substrate, the second vertically-oriented bit line select transistor comprising a second gate and the gate dielectric layer;
- a conductor disposed below the first vertically-oriented bit line select transistor and the second vertically-oriented bit line select transistor;
- a liner material layer;
- and
- a spacer dielectric layer,
- wherein the spacer dielectric layer and the gate dielectric layer are disposed between the conductor and each of the first gate and the second gate, and the liner material layer is disposed between the spacer dielectric layer and the gate dielectric layer and is disposed entirely below the first gate and the second gate.
4 more elements
Dependencies are inferred from the claim text.