Nonvolatile memory device having a vertical structure and a memory system including the same

A nonvolatile memory device, comprising:

• a first semiconductor layer comprising a first upper substrate and a second upper substrate adjacent to each other in a first direction and a memory cell array that comprises a plurality of memory blocks arranged in a second direction and first and second vertical structures, the first vertical structure comprising a plurality of first gate conductive layers stacked on the first upper substrate and a plurality of first pillars that pass through the first gate conductive layers and extend in a third direction perpendicular to the first and second directions, the second vertical structure comprising a plurality of second gate conductive layers stacked on the second upper substrate and a plurality of second pillars that pass through the second gate conductive layers and extend in the third direction;
• and
• a second semiconductor layer located under the first semiconductor layer in the third direction, wherein the second semiconductor layer comprises a lower substrate that comprises a plurality of row decoder circuits and a plurality of page buffer circuits,
• wherein the first vertical structure further comprises a first via area in which a first through-hole via passes through the first vertical structure and is connected to a first page buffer circuit, and a first partial block spaced apart from the first via area in the second direction, and
• the second vertical structure further comprises a second via area in which a second through-hole via passes through the second vertical structure and is connected to a second page buffer circuit, and a second partial block spaced apart from the second via area in the second direction.

A nonvolatile memory device, comprising:

• a first semiconductor layer including a first vertical structure and a second vertical structure, each of the first and second vertical structures including gate conductive layers stacked in a first direction;
• and
• a second semiconductor layer disposed under the first semiconductor layer along the first direction, the second semiconductor layer including a row decoder disposed under the first vertical structure and a page buffer disposed under the second vertical structure,
• wherein the first vertical structure includes a plurality of first partial blocks and a plurality of first via areas, the second vertical structure includes a plurality of second partial blocks and a plurality of second via areas, and at least one of the first partial blocks overlaps at least one of the second via areas in a second direction substantially perpendicular to the first direction.