Semiconductor memory devices

A semiconductor memory device, comprising:

• a stack structure including a plurality of layers vertically stacked on a substrate;
• and
• a second conductive line penetrating the stack structure and extending vertically,
• wherein each of the plurality of layers of the stack structure comprises:
• a semiconductor pattern extending in a second direction, the semiconductor pattern comprising a first impurity region, a second impurity region, and a channel region between the first and second impurity regions;
• a first conductive line electrically connected to the first impurity region and extending in a first direction intersecting the second direction;
• and
• a data storage element electrically connected to the second impurity region, and
• wherein the second conductive line is adjacent to the channel region of the semiconductor pattern.

A semiconductor memory device, comprising:

• a stack structure including a plurality of layers stacked vertically on a substrate, each of the plurality of layers including a plurality of memory cell transistors;
• a word line extending vertically from a top surface of the substrate and connected to gates of the memory cell transistors that are vertically stacked;
• a bit line extending in a first direction parallel to the top surface of the substrate and connected to a source of respective ones of the memory cell transistors in one layer of the plurality of layers;
• and
• a capacitor connected to a drain of respective ones of the memory cell transistors.