Memory device and method of manufacturing the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHAU-YAN LU, CHUN-YAO KO, FELIX YING-KIT TSUI
Life of this patent
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Abstract
A memory device is disclosed. The memory device includes: a first memory cell, including: a first transistor; a second transistor; and a first capacitor; a second memory cell, including: a third transistor; a fourth transistor; and a second capacitor; a third memory cell, including: a fifth transistor; a sixth transistor; and a third capacitor; and a fourth memory cell, including: a seventh transistor; an eighth transistor; and a fourth capacitor; wherein an electrode of the first capacitor, an electrode of the second capacitor, an electrode of the third capacitor, and an electrode of the fourth capacitor are electrically connected to a conductor. An associated manufacturing method is also disclosed.
Claims20
A memory device, comprising:
- a first memory cell, including:
- a first transistor;
- a second transistor;
- and
- a first capacitor coupled to the second transistor;
- a second memory cell, including:
- a third transistor;
- a fourth transistor;
- and
- a second capacitor coupled to the fourth transistor;
- a third memory cell, including:
- a fifth transistor;
- a sixth transistor;
- and
- a third capacitor coupled to the sixth transistor;
- and
- a fourth memory cell, including:
- a seventh transistor;
- an eighth transistor;
- and
- a fourth capacitor coupled to the eighth transistor;
- wherein an electrode of the first capacitor, an electrode of the second capacitor, an electrode of the third capacitor, and an electrode of the fourth capacitor are electrically connected to a conductor.
A memory device, comprising:
- a semiconductor substrate;
- a first well region of a first conductivity type in the semiconductor substrate;
- a second well region of a second conductivity type different from the first conductivity type in the semiconductor substrate;
- a third well region of the first conductivity type in the semiconductor substrate, wherein the second well region is between the first well region and the third well region;
- a first floating gate over the semiconductor substrate, the first floating gate overlapping the first well region and the second well region from a top view;
- a second floating gate over the semiconductor substrate, the second floating gate overlapping the first well region and the second well region from the top view;
- a third floating gate over the semiconductor substrate, the third floating gate overlapping the third well region and the second well region from the top view;
- and
- a fourth floating gate over the semiconductor substrate, the fourth floating gate overlapping the third well region and the second well region from the top view.
A method of manufacturing a memory device, comprising:
- obtaining a semiconductor substrate;
- forming a first well region of a first conductivity type in the semiconductor substrate;
- forming a second well region of a first conductivity type in the semiconductor substrate;
- forming a third well region of the first conductivity type in the semiconductor substrate;
- and
- forming a plurality of floating gates over the semiconductor substrate, wherein the floating gates overlaps the second well region from a top view.
Dependencies are inferred from the claim text.