Multi-cell per bit nonvolatile memory unit
AssigneeeMemory Technology Inc.
InventorsChih-Hsin Chen, Tsung-Mu Lai, Shih-Chen Wang
Life of this patent
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Abstract
A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.
Claims22
A multi-cell per bit nonvolatile memory (NVM) unit, comprising:
- a semiconductor substrate comprising a first oxide define (OD) region, a second oxide define (OD) region, and a third oxide define (OD) region separated from one another by a trench isolation region, wherein the first, second and third OD regions are in parallel to one another and extend along a first direction, and wherein the first OD region is situated between the second OD region and the third OD region;
- serially connected single-poly floating gate transistors disposed on the first OD region;
- wherein each of the serially connected single-poly floating gate transistors comprises a first floating gate extension continuously extending toward the second OD region along a second direction and adjacent to an erase gate region disposed in the second OD region;
- wherein each of the serially connected storage cells comprises a second floating gate extension continuously extending toward the third OD region along the second direction and wherein the second floating gate extension is capacitively coupled to a control gate region in the third OD region.
Dependencies are inferred from the claim text.