Stacked finfet eeprom

A semiconductor device, comprising:

• a first FET including a first channel region present in a first fin structure, the first FET connected to a first terminal and a common node;
• a second FET including a second channel region present in a second fin structure connected to a second terminal and the common node, wherein the first fin structure and second fin structure are stacked to provide that first sidewalls of the first fin structure are aligned with second sidewalls of the second fin structure;
• and
• an access transistor connected in series to the common node and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to a common floating gate of the first and second FETs to change a voltage of the common floating gate.

A semiconductor structure, comprising:

• a stack of at least a first fin structure and a second fin structure;
• first conductivity type source/drain regions present on opposing ends of a first channel region of the first fin structure;
• second conductivity type source/drain regions present on opposing ends of a second channel region of the second fin structure;
• and
• a single floating gate present on both of the first and second channel regions of the first and second fin structures, wherein the single floating gate provides electrical communication between a first field effect transistor including the first fin structure and a second field effect transistor including the second fin structure in an EEPROM memory device.