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US 2019/0164973 A1Published application
Memory array comprising memory cells of z2-fet type
AssigneeSTMicroelectronics S.r.l.
InventorsHassan EL DIRANI, Thomas BEDECARRATS, Philippe GALY
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Abstract
A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.
Claims23
A memory array, comprising:
- a plurality of memory cells of Z2-FET type;
- and
- a corresponding plurality of MOS-type selection transistors;
- wherein each memory cell comprises a first region of a first conductivity type in common with a drain region of the first conductivity type of a corresponding one of the MOS-type selection transistors;
- and
- wherein the MOS-type selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.
3 more elements
A memory cell, comprising:
- a Z2-FET type memory device including an anode region, a cathode region and a lightly-doped region separating the anode region from the cathode region;
- and
- a MOS-type selection transistor connected to the Z2-FET type memory device;
- wherein the cathode region of the Z2-FET type memory device is also a drain region of the MOS-type selection transistor;
- and
- wherein a width of the anode region and the lightly-doped region is smaller than a width of the cathode region, said widths being perpendicular to a direction extending between the drain region and a source region of the MOS-type selection transistor.
3 more elements
A memory cell, comprising:
- a Z2-FET type memory device including an anode region, a cathode region and a lightly-doped region separating the anode region from the cathode region;
- and
- a MOS-type selection transistor connected to the Z2-FET type memory device;
- wherein the anode region of the Z2-FET type memory device is also a drain region of the MOS-type selection transistor;
- and
- wherein a width of the cathode region and lightly-doped region is smaller than a width of the anode region, said widths being perpendicular to a direction extending between the drain region and source region of the MOS-type selection transistor.
3 more elements
A method of manufacturing a memory array, comprising:
- forming a plurality of memory cells of Z2-FET type and a plurality of MOS-type selection transistors arranged in rows and in columns, comprising:
- forming each memory cell to include a first region of a first conductivity type;
- forming each MOS-type selection transistor to include a drain region in common with the first region of the memory cell and with all selection transistors of a same column;
- forming a source region common to all the MOS-type selection transistors of the same column;
- and
- forming a gate region common to all the MOS-type selection transistors of the same column.
3 more elements
Dependencies are inferred from the claim text.