Integrated semiconductor device with 2d material layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng-Yi PENG, Chun-Chieh LU, Meng-Hsuan HSIAO, Ling-Yen YEH, Carlos H. DIAZ, Tung-Ying LEE
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Abstract
An integrated semiconductor device includes a first semiconductor device, an ILD layer and a second semiconductor device. The semiconductor device has a first transistor structure. The ILD layer is over the semiconductor device and has a thickness in a range substantially from 10 nm to 100 nm. The second semiconductor device is over the ILD layer and has a 2D material layer as a channel layer of a second transistor structure thereof.
Claims20
An integrated semiconductor device, comprising:
- a first semiconductor device having a first transistor structure;
- an inter-layer dielectric (ILD) layer over the first semiconductor device, wherein a thickness of the ILD layer is in a range substantially from 10 nm to 100 nm;
- and
- a second semiconductor device having a second transistor structure, wherein the second semiconductor device has a two-dimensional (2D) material layer formed over the ILD layer as a channel layer of the second transistor structure.
A method of fabricating an integrated semiconductor device, the method comprising:
- providing a semiconductor device, the semiconductor device having a first transistor structure;
- forming an inter-layer dielectric (ILD) layer over the semiconductor device, wherein a thickness of the ILD layer is in a range substantially from 10 nm to 100 nm;
- forming a two-dimensional (2D) material layer over the ILD layer;
- patterning the 2D material layer to form a channel layer of a second transistor structure;
- forming a source electrode and a drain electrode of the second transistor structure respectively at two opposite ends of the patterned 2D material layer;
- forming a gate dielectric layer of the second transistor structure over the patterned 2D material layer, the source electrode and the drain electrode;
- and
- forming a gate electrode of the second transistor structure over the gate dielectric layer and laterally between the source electrode and the drain electrode.
A method of fabricating an integrated semiconductor device, the method comprising:
- providing a semiconductor device, the semiconductor device having a first transistor structure;
- forming an inter-layer dielectric (ILD) layer over the semiconductor device, wherein a thickness of the ILD layer is in a range substantially from 10 nm to 100 nm;
- forming a first conductive plug through the ILD layer and contacting a gate of the first transistor structure;
- forming a second conductive plug through the ILD layer and contacting a drain of the first transistor structure;
- forming a gate stack over the ILD layer and contacting the first conductive plug;
- forming a two-dimensional (2D) material layer over the gate stack and the ILD layer and contacting the second conductive plug as a channel layer of a second transistor structure;
- and
- forming a conductive via that contacts the 2D material layer, wherein the second conductive plug and the conductive via are respectively at opposite sides laterally relative to the gate stack.
Dependencies are inferred from the claim text.