Structure with embedded memory device and contact isolation scheme

A method of fabricating an integrated circuit, comprising:

• forming a source and a drain on a fin active region of a semiconductor substrate;
• depositing an interlayer dielectric (ILD) layer on the source and drain;
• patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively;
• forming a dielectric material layer in the first contact hole;
• forming a dielectric feature in the first contact hole, wherein the dielectric feature has a bottom surface directly contacting the source and sidewalls directly contacting the first dielectric material layer;
• and
• forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively, wherein the forming of the dielectric material layer in the first contact hole includes
• depositing the dielectric material layer in the first contact hole;
• and
• performing an anisotropic etching process to remove a bottom portion of the dielectric material layer within the first contact hole such that the source is exposed.

A method, comprising:

• forming a metal gate stack on a fin active region of a semiconductor substrate;
• forming a source and a drain on the fin active region, the source and drain being doped with a same type of dopant;
• forming a silicide layer self-aligned on the metal gate stack;
• forming an interlayer dielectric (ILD) layer on the source and the drain;
• patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively;
• forming a dielectric material layer in the first contact hole;
• and
• forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively, wherein the first conductive feature is separated from the source by the dielectric material layer and the second conductive feature directly contacts the drain.

A method of fabricating an integrated circuit, comprising:

• forming a source and a drain on a fin active region of a semiconductor substrate;
• depositing an interlayer dielectric (ILD) layer on the source and drain;
• patterning the ILD layer to form a through hole to expose the drain;
• patterning the ILD to form a recess hole vertically aligning with the source and with a bottom portion of the ILD remained within the recess hole;
• and
• depositing to form a first conductive feature in the recess hole and a second conductive feature in the through hole,
• wherein the first conductive feature is separated from the source by the bottom portion of the ILD and the second conductive feature directly contacts the drain.