3d stacked dies with disparate interconnect footprints

A semiconductor chip device, comprising:

• a first semiconductor chip having a front side and a back side, and plural through chip vias and I/O structures, the through chip vias having a first footprint
• plural second semiconductor chips stacked on the back side of the first semiconductor chip, a lowermost of the second semiconductor chips including plural interconnects having a second footprint larger than the first footprint;
• the back side including a back side redistribution layer (RDL) structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias, the back side RDL structure including one or more interconnect layers that consist of interlevel dielectric material and conductor structures;
• and
• the front side including a front side RDL structure connected to the through chip vias and providing fanned-out pathways to the I/O structures.

A method of manufacturing a semiconductor chip device, comprising:

• fabricating a back side redistribution layer structure (RDL) on a back side of a first semiconductor chip, the first semiconductor chip having plural through-chip vias with a first footprint, the back side being configured to have a second semiconductor chip stacked thereon, the second semiconductor chip including plural interconnects having a second footprint larger than the first footprint;
• the back side RDL structure is configured to connect to connect to the interconnects and provide fanned-in pathways to the through chip vias, the back side interconnect structure including one or more interconnect layers that consist of interlevel dielectric material and conductor structures;
• fabricating plural I/O structures on a front side of the first semiconductor chip;
• and
• fabricating a front side RDL structure on the front side that electrically connects to the through chip vias and provides fanned-out pathways to the I/O structures.