Fan-out semiconductor package

A fan-out semiconductor package comprising:

• a frame including a plurality of insulating layers and having a recess portion penetrating a portion of the frame, at least one of the plurality of insulating layers not penetrated through by the recess portion;
• first semiconductor chip and second semiconductor chips and disposed in the recess portion, each of the first and second semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the at least one of the plurality of insulating layers not penetrated through by the recess portion;
• an encapsulant covering at least portions of the first and second semiconductor chips and filling at least portions of the recess portion;
• a connection member disposed on the frame and the active surfaces of the first and second semiconductor chip and including a redistribution layer;
• first wire posts disposed between the connection pads of the first semiconductor chip and the redistribution layer, and electrically connecting the connection pads of the first semiconductor chip and the redistribution layer to each other;
• and
• second wire posts disposed between the connection pads of the second semiconductor chip and the redistribution layer, and electrically connecting the connection pads of the second semiconductor chip and the redistribution layer to each other,
• wherein each of the first wire posts includes a body portion disposed on one of the connection pads of the first semiconductor chip, and a lead portion having a width less than that of the body portion thereof and disposed between the body portion thereof and the redistribution layer,
• each of the second wire posts includes a body portion disposed on one of the connection pads of the second semiconductor chip, and a lead portion having a width less than that of the body portion thereof and disposed between the body portion thereof and the redistribution layer, and
• a thickness of the first semiconductor chip is greater than a thickness of the second semiconductor chip, and a height of the lead portion of each of the first wire posts is less than a height of the lead portion of each of the second wire posts.