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US 2019/0164924 A1Published application
Redistribution layer (rdl) layouts for integrated circuits
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng-Yuan Li, Kuo-Cheng Lee, Yun-Wei Cheng, Yen-Liang Lin
Life of this patent
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Abstract
Exemplary embodiments for redistribution layers of integrated circuits are disclosed. The redistribution layers of integrated circuits of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.
Claims21
A semiconductor structure, comprising:
- a first integrated circuit comprising first electronic circuitry;
- a second integrated circuit comprising second electronic circuitry, the first electronic circuitry and second electronic circuitry being situated within a first semiconductor stack having a plurality of conductive layers interdigitated with a plurality of non-conductive layers situated on a first semiconductor substrate;
- and
- a first redistribution layer situated within a conductive layer from among the plurality of conductive layers of the first semiconductor stack, the first redistribution layer including a first array of conductive contacts on the first integrated circuit and a second array of conductive contacts on the second integrated circuit, the first array of conductive contacts and the second array of conductive contacts extending along a first direction, the first integrated circuit being adjoined with the second integrated circuit in a second direction substantially perpendicular to the first direction, a first adjoin boundary between the first integrated circuit and the second integrated circuit being substantially parallel with the first direction, wherein at most one of the first array of conductive contacts and the second array of conductive contacts is situated between the first electronic circuitry and the second electronic circuitry and extends along the first adjoin boundary, wherein the first array and the second array are the only conductive contacts between the first electronic circuitry and the second electronic circuitry;
- and
- a second semiconductor substrate comprising a second semiconductor stack and a second redistribution layer on the second semiconductor stack, wherein the second redistribution layer is bonded with and electrically connected to the first redistribution layer.
3 more elements
10-20. (canceled)
A method, comprising:
- fabricating a first semiconductor wafer comprising a first integrated circuit, a second integrated circuit and a first redistribution layer, the first integrated circuit comprising first electronic circuitry, the second integrated circuit comprising second electronic circuitry, the first redistribution layer including a first array of conductive contacts on the first integrated circuit and a second array of conductive contacts on the second integrated circuit, the first array of conductive contacts and the second array of conductive contacts extending along a first direction, the first integrated circuit being adjoined with the second integrated circuit in a second direction substantially perpendicular to the first direction, and a first adjoin boundary being between the first integrated circuit and the second integrated circuit, wherein there are no conductive contacts between the first array of conductive contacts and the second array of conductive contacts;
- and
- fabricating a second semiconductor wafer comprising a semiconductor stack and a second redistribution layer on the semiconductor stack, the second redistribution layer is bonded with and electrically connected to the first redistribution layer;
- and
- bonding the first semiconductor wafer and the second semiconductor wafer.
2 more elements
A method, comprising:
- fabricating a first semiconductor wafer comprising a first integrated circuit, a second integrated circuit and a first redistribution layer, the first integrated circuit comprising first electronic circuitry, the second integrated circuit comprising second electronic circuitry, the first redistribution layer including a first array of conductive contacts on the first integrated circuit and a second array of conductive contacts on the second integrated circuit, the first array of conductive contacts and the second array of conductive contacts extending along a first direction, the first integrated circuit being adjoined with the second integrated circuit in a second direction substantially perpendicular to the first direction, wherein the first array of conductive contacts and the second array of conductive contacts are aligned with each other in the second direction, the first array of conductive contacts is formed between the first electronic circuitry and the second electronic circuitry, and the second electronic circuitry is formed under an area between the first array of conductive contacts and the second array of conductive contacts, wherein the conductive contacts of the first array of conductive contacts are the only conductive contacts between the first electronic circuitry and the second electronic circuitry;
- and
- fabricating a second semiconductor wafer comprising a semiconductor stack and a second redistribution layer on the semiconductor stack, the second redistribution layer is bonded with and electrically connected to the first redistribution layer;
- and
- bonding the first semiconductor wafer and the second semiconductor wafer.
2 more elements
Dependencies are inferred from the claim text.