Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsAe-nee JANG, KyungSeon HWANG, SunWon KANG
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.
Claims21
-20. (canceled)
A semiconductor package comprising:
- a substrate;
- a first chip on the substrate, the first chip has first through-electrodes penetrating the first chip;
- a second chip on the first chip;
- bumps between the first chip and the second chip;
- and
- an underfill filling a space between the first chip and the second chip,
- wherein the bumps include:
- first bumps spaced apart from each other in a first direction parallel to a top surface of the first chip, the first bumps being electrically connected to the through-electrodes, respectively, and
- at least one second bump between the first bumps, the at least one second bump being electrically insulated from the through-electrodes,
- wherein the first bumps and the at least one second bump constitute one row in the first direction,
- wherein a level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same level as levels of bottom surfaces of the first bumps from the top surface of the substrate, and
- wherein the underfill covers a space between the first bumps and covers a space between the first bumps and the at least one second bump.
A semiconductor package, comprising:
- a substrate;
- a first chip and second chip on the first chip, each of the first chip and the second chip include through-electrodes penetrating thereof;
- a plurality of bumps between the first chip and the second chip, the bumps including a plurality of first bumps that have respective electrical connections to through-electrodes and including a plurality of second bumps interspersed between the first bumps, the second bumps being mounted on an insulating region of a top surface of the first chips, the first and second bumps being spaced at a regular pitch;
- an underfill layer between he first chip and the second chip, the underfill layer contacting the first and second bumps;
- and
- an insulating pattern on the substrate,
- wherein the first bumps and the second bumps constitute one row in a first direction parallel to the top surface of the first chip,
- wherein a level of a bottom surface of the second bumps from the top surface of the first chip is a substantially same level as levels of bottom surfaces of the first bumps from the top surface of the first chip, and
- wherein the insulating pattern covers a space between the first bumps and covers a space between the first bumps and the second bumps.
Dependencies are inferred from the claim text.