Pad structure and manufacturing method thereof in semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHUNG-SHU HUANG, MING-CHYI LIU
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Abstract
A method of manufacturing a semiconductor device includes: forming a memory cell on a substrate; forming a conductive pad region to electrically couple to the memory cell; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region; and etching the second passivation layer to expose a second area of the conductive pad region.
Claims20
A method of manufacturing a semiconductor device, comprising:
- forming a memory cell on a substrate;
- forming a conductive pad region to electrically couple to the memory cell;
- depositing a dielectric layer over the conductive pad region;
- forming a first passivation layer over the dielectric layer;
- etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region;
- forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region;
- and
- etching the second passivation layer to expose a second area of the conductive pad region.
A semiconductor device, comprising:
- a substrate;
- a conductive pad region electrically coupled to the substrate;
- a first dielectric layer over the conductive pad region;
- a passivation layer over the first dielectric layer, wherein the passivation layer comprises a lateral-extending portion covering the first dielectric layer and a vertical-extending portion on a sidewall of the first dielectric layer,
- wherein the lateral-extending portion and the vertical-extending portion of the passivation layer are joined through a vertically extending boundary.
A semiconductor structure, comprising:
- a memory cell;
- and
- a pad structure electrically coupled to the memory cell, the pad structure comprising:
- a conductive pad region over the memory cell;
- a first dielectric layer disposed over the conductive pad region;
- and
- a first passivation layer over the first dielectric layer and exposing an area of the conductive pad region, wherein a vertical portion of the first passivation layer comprising a substantially equal thickness covers a sidewall of the first dielectric layer and contacts the exposed area of the conductive pad region.
Dependencies are inferred from the claim text.