Semiconductor package

A semiconductor package comprising:

• an interposer having a first surface having a plurality of pads provided thereon and a second surface opposing the first surface and including a first redistribution layer connected to the plurality of pads;
• a semiconductor chip having an active surface having connection electrodes disposed thereon and an inactive surface opposing the active surface and disposed on the interposer so that the inactive surface faces the second surface of the interposer;
• an encapsulant disposed on the second surface of the interposer, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region positioned in the vicinity of the semiconductor chip;
• a second redistribution layer including connection vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the first redistribution layer, and wiring patterns disposed on the encapsulant and having integrated structures with the connection vias and the through-vias;
• and
• a connection member having a first surface disposed on the encapsulant and a second surface opposing the first surface and having electrical connection structures disposed thereon, and including a third redistribution layer connected to the second redistribution layer and the electrical connection structures,
• wherein the first redistribution layer has a plurality of first wiring patterns and first vias connected to the plurality of first wiring patterns, first wiring patterns adjacent to the first surface of the interposer among the plurality of first wiring patterns protrude from the interposer, and first wiring patterns adjacent to the second surface of the interposer among the plurality of first wiring patterns are embedded in the interposer.