Semiconductor device integrating backside power grid and related integrated circuit and fabrication method

An integrated circuit, comprising:

• a substrate;
• a dielectric region situated on the substrate;
• a first fin field-effect transistor, comprising a first source region, a first gate region and a first drain region situated on the dielectric region;
• a conductive rail situated within the dielectric region, the conductive rail being electrically connected to a first terminal region selected from among the first source region, the first gate region and the first drain region;
• and
• a conductive structure penetrating through the substrate and formed under the conductive rail, the conductive structure being electrically connected to the conductive rail.

A method for forming a non-planar semiconductor device, comprising:

• forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device;
• forming a dielectric region on the front side of the substrate, wherein the dielectric region comprises a conductive rail buried within the dielectric region and being in parallel with the fin structure;
• forming a first opening in the dielectric region to expose the conductive rail;
• forming a plurality of conductive regions on the dielectric region, wherein one of the plurality of conductive regions contacts the conductive rail through the first opening;
• etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail;
• filling a first conductive material into the second opening to form a through-substrate via in the substrate.