Carrier substrate and method of manufacturing semiconductor package using the same
AssigneeSamsung Electro-Mechanics Co., Ltd.
InventorsJae Ean LEE, Tae Sung JEONG, Young Gwan KO, Ik Jun CHOI, Jung Soo BYUN
Life of this patent
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Abstract
A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.
Claims29
A carrier substrate, comprising:
- a core layer;
- a first metal layer disposed on the core layer;
- a release layer disposed on the first metal layer;
- and
- a second metal layer disposed on the release layer,
- wherein at least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer.
A method of manufacturing a semiconductor package, comprising:
- providing a carrier substrate including a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer, wherein at least one layer among the first metal layer, the release layer, and the second metal layer forms a plurality of unit pattern portions having an area smaller than an area of the core layer;
- forming an interposer on each unit pattern portion of the plurality of unit pattern portions;
- separating the carrier substrate and the interposer between the plurality of unit pattern portions to isolate the plurality of unit pattern portions from each other;
- disposing a plurality of semiconductor chips on the interposer of each unit pattern portion having been separated;
- forming an encapsulant on the interposer of each respective unit pattern portion having been separated to encapsulate the plurality of semiconductor chips on each interposer;
- trimming each unit pattern portion having been separated and having the encapsulant, to allow one or more of the plurality of semiconductor chips to be isolated from each other;
- and
- separating each unit pattern portion that has been trimmed from each interposer having been separated.
A carrier substrate, comprising:
- a core layer;
- and
- a plurality of unit pattern portions disposed on the core layer to be spaced apart from each other,
- wherein each unit pattern portion includes a release layer and metal layers disposed on a surface of the release layer facing away from the core layer.
A method comprising:
- forming a first metal layer on an upper surface of a core layer;
- forming a release layer on an upper surface of the first metal layer;
- forming a second metal layer to cover an entire upper surface of the release layer, wherein the release layer and second metal layer are patterned to form unit pattern portions spaced apart from each other;
- and
- cutting the core layer having the first metal layer, release layer, and second metal layer formed thereon at locations between the unit pattern portions.
Dependencies are inferred from the claim text.