Semiconductor device and method of manufacture

A method comprising:

• forming a first conductive feature and a second conductive feature over an interconnect structure, the interconnect structure being over a substrate;
• forming a test pad over and electrically connected to the first conductive feature;
• probing the test pad to determine an electrical connectivity between the test pad and the interconnect structure;
• forming a dielectric layer over the test pad and the second conductive feature;
• forming a first bond pad through the dielectric layer, wherein the first bond pad contacts the test pad;
• and
• forming a second bond pad through the dielectric layer, wherein the second bond pad contacts the second conductive feature, and wherein the second bond pad has a larger height than the first bond pad.

An integrated circuit comprising:

• a first metal feature and a second metal feature disposed in a single top metal layer over a substrate;
• a test pad over and electrically connected to the first metal feature;
• a first passivation layer over the second metal feature and the test pad and covering a top surface and side surfaces of the test pad;
• a first via penetrating through the first passivation layer to contact the test pad;
• and
• a second via penetrating through the first passivation layer to contact the second metal feature.