System and method for in-line processing control
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsiao-Hua PENG, Hann-Ru Cheng
Life of this patent
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Abstract
Disclosed is an in-line processing control method and system. In one embodiment, the n method comprising: conducting a critical dimension (CD) inspection on a first wafer; generating a first CD map of the first wafer; determining a first temperature profile map and a first plasma processing configuration based on the first CD map of the first wafer, wherein the first plasma processing configuration comprises a first temperature profile map, a first etch time and a first plasma processing condition; and configuring a plasma etching process with the first plasma processing configuration for processing the first wafer.
Claims21
An in-line processing control method comprising:
- conducting a critical dimension (CD) inspection on a first wafer;
- generating a first CD map of the first wafer;
- determining a first temperature profile map and a first plasma processing configuration based on the first CD map of the first wafer, wherein the first plasma processing configuration comprises a first temperature profile map, a first etch time and a first plasma processing condition;
- and
- configuring a plasma etching process with the first plasma processing configuration for processing the first wafer.
An in-line processing control system comprising:
- a patterning processing station;
- an in-line critical-dimension (CD) inspection station, wherein the in-line CD inspection station is configured to automatically collect at least one CD value of at least one pattern on a first wafer to create a first CD map;
- and
- a plasma processing station, wherein the plasma processing station comprises a plurality of temperature control elements on a wafer stage, wherein the plurality of temperature control elements is configured based on the first CD map.
An in-line processing control comprising:
- a first processing station, wherein the first processing station is configured to produce at least one feature on a semiconductor wafer;
- an inspection station, wherein the inspection station is configured to generate a first critical dimension (CD) map of the at least one feature on the semiconductor wafer;
- and
- a second processing station, wherein the second processing station is configured to provide a second processing on the semiconductor wafer and comprises a plurality of temperature control elements on a wafer stage.
Dependencies are inferred from the claim text.