US 2019/0164845 A1 · SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Abstract

The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device includes a substrate; two fins located on the substrate and extending along a first direction; an isolation material layer surrounding the fins, comprising a first isolation regions located at an end region between the two fins along the first direction, and a second isolation region located at sides of the fins along a second direction that is different from the first direction, wherein an upper surface of the first isolation region substantially align with an upper surfaces of the fins, and an upper surface of the second isolation region is lower than the upper surface of the fins; and a first insulating layer on the first isolation region

Claims7

Dependent claims

A semiconductor device, comprising:

a substrate;
a fin located on the substrate and extending along a first direction;
an isolation material layer surrounding the fin, comprising:
a first isolation region located at an end region of the fin along the first direction;
and
a second isolation region located at sides of the fin along a second direction that is different from the first direction,
wherein an upper surface of the first isolation region substantially align with an upper surface of the fin, and an upper surface of the second isolation region is lower than the upper surface of the fin;
and
a first insulating layer on the first isolation region.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/263,441Filed 31 Jan 2019

Priority

CN 201610899633.X17 Oct 2016

Published

30 May 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain

Semiconductor device and manufacturing method therefor

Life of this patent

Semiconductor device and manufacturing method therefor

Life of this patent

Abstract

Claims7