Semiconductor structure with cutting depth control and method for fabricating the same

A method for fabricating a semiconductor device, wherein the method comprises:

• forming a plurality of fins respectively protruding from a substrate;
• forming trench isolations between every two adjacent fins;
• forming a dummy gate structure crossing the fins;
• growing source/drain devices on both sides of the dummy gate structure on the fins;
• depositing an inter-layer dielectric layer crossing each of the fins on each of both sides of the dummy gate structure and enclosing the source/drain devices;
• removing the dummy gate structure, thereby forming a gate-line opening;
• depositing a metal gate structure in the gate-line opening;
• performing a replacement operation to replace a plurality of portions of the inter-layer dielectric layer with an isolation material, thereby forming a plurality of isolation portions respectively contacting each of both sides of the metal gate structure between every two adjacent fins;
• and
• performing a metal gate cut operation on a cut region extending through the metal gate structure to adjoined one of the isolation portions until the trench isolations are exposed by a first opening formed in the metal gate structure, wherein an etchant of the metal gate cut operation has a lower etching selectivity with respect to the isolation portion than to the metal gate structure, such that a first depth of the first opening is greater than a second depth of a second opening formed in the isolation portion.

A semiconductor structure, comprising:

• a semiconductor substrate;
• a first fin and a second fin respectively protruding from the semiconductor substrate, wherein the first fin includes a first gate region and first source/drain regions, and the second fin includes a second gate region and second source/drain regions;
• a plurality of source/drain devices epitaxially grown on the first source/drain regions and the second source/drain regions;
• a metal gate structure extending from the first fin to the second fin, wherein the metal gate structure is over and around the first gate region and the second gate region, and the metal gate structure includes:
• a first separation plug between the first fin and the second fin, wherein the first separation plug has a first depth;
• and
• an inter-layer dielectric layer deposited between and over the adjacent source/drain devices, wherein the inter-layer dielectric layer includes:
• an isolation portion including a second separation plug, wherein the second separation plug has a second depth smaller than the first depth, and a bottom of the second separation plug is elevated higher than the source/drain devices.