Liner structure in interlayer dielectric structure for semiconductor devices

Abstract

Semiconductor device structures having a liner layer in an interlayer dielectric structure are provided. In one example, a semiconductor device includes an active area on a substrate, the active area comprising a source/drain region, a gate structure over the active area, the source/drain region being proximate the gate structure, a spacer feature along a sidewall of the gate structure, a contact etching stop layer on the spacer feature, a liner oxide layer on the contact etching stop layer, and an interlayer dielectric layer on the liner oxide layer, wherein the liner oxide layer has an oxygen concentration level greater than the interlayer dielectric layer.

Dependencies are inferred from the claim text.