Damascene plug and tab patterning with photobuckets for back end of line (beol) spacer-based interconnects

A back end of line (BEOL) metallization layer for a semiconductor structure, the BEOL metallization layer comprising:

• an inter-layer dielectric (ILD) layer disposed above a substrate;
• a plurality of conductive lines disposed in the ILD layer along a first direction, the plurality of conductive lines each having a width of 10 nanometers or less;
• and
• a conductive tab disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction.

A method of fabricating a back end of line (BEOL) metallization layer for a semiconductor structure, the method comprising:

• forming an inter-layer dielectric (ILD) layer above a substrate;
• forming a first plurality of photobuckets above the ILD layer, the first plurality of photobuckets defining all possible dielectric plug locations for the BEOL metallization layer;
• removing fewer than all of the first plurality of photobuckets and retaining one or more of the first plurality of photobuckets in select dielectric plug locations;
• forming a second plurality of photobuckets above the ILD layer, the second plurality of photobuckets defining all possible conductive tab locations for the BEOL metallization layer;
• removing fewer than all of the second plurality of photobuckets in select conductive tab locations and retaining one or more of the second plurality of photobuckets;
• subsequent to removing fewer than all of the first plurality of photobuckets and removing fewer than all of the second plurality of photobuckets, transferring an image including the select dielectric plug locations and the select conductive tab locations to the ILD layer;
• and
• forming a plurality of conductive lines, one or more dielectric plugs, and one or more conductive tabs in the ILD layer.