Method of forming field effect transistor (fet) circuits, and forming integrated circuit (ic) chips with the fet circuits

A method of forming an Integrated Circuit (IC) chip with a plurality of field effect transistor (FET) circuits, said method comprising:

• forming a gate dielectric layer on a semiconductor surface of a wafer;
• forming a plurality of gates on said a gate dielectric layer;
• forming gate sidewall spacers alongside each gate, said gate sidewall spacers being formed of a second dielectric;
• forming source/drain region adjacent to said each gate sidewall;
• forming an insulation layer on said wafer, said insulation layer filling between said gate sidewall spacers;
• etching self-aligned source/drain contacts at a plurality of locations with a combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch, etched said source/drain contacts being through said insulation layer and said gate dielectric layer to said source/drain regions;
• filling the self-aligned contacts with conductive material, a contact to a respective source/drain region being formed;
• and
• forming a plurality of wiring layers, wires in said plurality of wiring layers connecting FETs into circuits to and through said self-aligned contacts.