Semiconductor structure and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Wei SU, Fu-Ting YEN, Ting-Ting CHEN, Teng-Chun TSAI
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Abstract
A method includes forming a gate stack and an interlayer dielectric (ILD) over a substrate, wherein the interlayer dielectric is adjacent to the gate stack; forming an inhibitor covering the interlayer dielectric such that the gate stack is exposed from the inhibitor; performing a deposition process to form a conductive layer over the gate stack until the conductive layer starts to form on the inhibitor, in which the deposition process has a deposition selectivity for the gate stack with respect to the inhibitor; and performing an etching process to remove a portion of the conductive layer over the inhibitor.
Claims20
A method, comprising:
- forming a gate stack and an interlayer dielectric (ILD) over a substrate, wherein the interlayer dielectric is adjacent to the gate stack;
- forming an inhibitor covering the interlayer dielectric such that the gate stack is exposed from the inhibitor;
- performing a deposition process to form a conductive layer over the gate stack until the conductive layer starts to form on the inhibitor, wherein the deposition process has a deposition selectivity for the gate stack with respect to the inhibitor;
- and
- performing an etching process to remove a portion of the conductive layer over the inhibitor.
A method, comprising:
- forming a gate stack and an interlayer dielectric (ILD) over an underlying structure, wherein the interlayer dielectric is adjacent to the gate stack;
- selectively forming an inhibitor over the gate stack;
- performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD until the dielectric layer starts to form on the inhibitor, wherein the dielectric layer has greater growing rate on the ILD than on the inhibitor;
- and
- performing an atomic layer etching (ALE) process to remove the dielectric layer until a top surface of the inhibitor is exposed.
A semiconductor structure, comprising:
- a gate stack;
- an interlayer dielectric layer surrounding the gate stack;
- a plurality of gate spacers respectively between the gate stack and the interlayer dielectric, wherein the gate spacers define a recess over the gate stack;
- a contact in the recess;
- and
- an inhibitor between the contact and one of the gate spacers.
Dependencies are inferred from the claim text.